ME Embedded System and VLSI Design at D. Y. Patil College of Engineering Pune 2024: Admission, Cutoff & Fee structure

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#Admission2024
D. Y. Patil College of Engineering

ME Embedded System and VLSI Design at D. Y. Patil College of Engineering Pune 2024: Admission, Cutoff & Fee structure

Pune, Maharashtra
AICTE, NBA
Estd 1984
Private College

D. Y. Patil College of Engineering Master of Engineering [ME] (Embedded System and VLSI Design)

Duration
2 Years
Level
Post Graduation
Eligibility
Graduation with 50%+ GATE
Course Type
Degree
Course Mode
Full Time
Fees
₹ 121,307

D. Y. Patil College of Engineering ME Embedded System and VLSI Design Fees

Year Tution Fees Admission Fees Registration Fees Exam Fees Course Fees Total Fees
1 ₹ 121307 - - - - ₹ 121307
2 ₹ 121307 - - - - ₹ 121307

Top Exams Accepted by D. Y. Patil College of Engineering

JEE Main - Joint Entrance Exam Main

Online Mode
Registration Date:14 Dec,2023
Exam Date:24 Feb,2024
Results Date:15 Apr,2024

GATE - Graduate Aptitude Test in Engineering

Online Mode
Registration Date:30 Aug,2023
Exam Date:11 Feb,2024
Results Date:16 Mar,2024

MHT CET - Maharashtra Health Sciences and Technical Common Entrance Test

Offline Mode
Registration Date:8 Mar,2024
Exam Date:11 May,2024
Results Date:1 Jul,2024
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